1. Field of the Invention
This invention relates to a semiconductor device and, in particular, to a semiconductor device which is capable of trimming timing of an output signal.
2. Description of the Related Art
It is a recent trend that a clock rate of an MPU (Micro-Processing Unit) or logic circuits connected thereto have been increased year by year. Recent requirements have been directed to a circuit operated at 100 to 300 MHz. In this case, a clock must be generated which has a clock period of 3 to 10 ns and the MPU generates each signal on the basis of this clock. Moreover, it would be expected that the clock rate will become higher in the future.
Here, when a signal passes through a logic gate, a transmission speed of the signal, namely, a delay time, is based on various variations. Such variations appear in dependency upon a manufacturing process of a transistor included in the logic gate (namely, a variation of a threshold voltage Vt or a gate length which determine performance of the transistor), driving ability, a parasitic capacity connected to a load, an operating temperature, or an operating voltage. At any rate, the variation of the delay time does not always fall within a predetermined range. When the delay time is fluctuated, a semiconductor device can not correctly operate because data is not correctly latched or a result of logical operation becomes incorrect.
On the other hand, it is requested that timing of a signal from a semiconductor device must fall within a predetermined range which is determined in relation to a peripheral device connected to the semiconductor device. That is, to guarantee operations between the semiconductor devices (devices on a board), a signal which sent from a semiconductor device to another semiconductor device lasts for a duration during which the signal can be certainly received by the other semiconductor device. In addition, a minimum delay time and a maximum delay time should be satisfied in connection with a reference signal.
If the signal does not satisfy conditions related to the delay times mentioned above and a change in the signal output from the semiconductor device is earlier than the reference signal, the other semiconductor device which must receive the signal can not fetch the signal and, as a result, receives the next following signal instead of the signal in question. On the other hand, if a change in the signal output from the semiconductor device is later than the reference signal, the other semiconductor device can not fetch or receive the signal but might wrongly receive a previous signal preceding the signal in question.
Under the circumstances, verification of each semiconductor should be made before shipment by a manufacturer about whether or not timing of output signal falls within the predetermined duration. Occurrence of a lot of defective products is undesirable because it leads to high cost of the semiconductor device. In particular, since a recent increase of the clock rate overwhelms an amount of a reduction rate of a variation in the manufacturing process, it is very difficult to establish the predetermined minimum and maximum output delay times.
Taking the above into consideration, even if any fluctuation takes place during a manufacturing process, it is important to design a semiconductor device so that the delay time of the semiconductor may fall within the predetermined range. For example, when a semiconductor device is operated by the clock of 10 MHz, no problem takes place even if fluctuation of 10 ns occurs in the clock. This is because a clock period is equal to 100 ns.
On the other hand, when the clock of 100 MHz is used for the semiconductor device, fluctuation of the delay time of 10 ns causes an undesirable operation to occur since the delay time becomes equal to the clock period of 10 ns.
To resolve the problem, disclosure is made, for example, in Japanese Laid-Open Publication No. H9-181580 (namely, 181580/1997) about a semiconductor which controls a delay time by improving a configuration of a circuit. In this event, a delay circuit which has a plurality of delay gates connected in series is incorporated in a semiconductor device and, in front of each delay gate, an AND gate which switches according to a control signal is provided. With this structure, a selected one of the delay gates is supplied to an external circuit by measuring a delay value required when the delay circuit is incorporated in the system, and the AND gate is closed to block passage of a pulse when an unused delay gate is sought and detected.
However, the delay circuit must have an expensive tester for measuring the delay value since the delay value must be measured by connecting the tester to the outside of the semiconductor device. In addition, the register in the semiconductor device must be set to adjust the delay time based on the measurement. In particular, when there is need to measure a delay time of the semiconductor device which operates at a high-speed, use should be made of a very expensive tester.
Moreover, when verification is performed before shipment, shipment processes become complicated due to addition of such a verification process and, as a result, a working time becomes long. This results in an increase of a cost of the goods.
Also a verification result obtained in a verification environment is not always identical with a result obtained in a practical use, because a practical temperature and a source voltage in practical use are often different from those of the verification environment.
In a usual verification process, the verification is performed by changing only a source voltage at a normal temperature to reduce a time of the verification. When the verification is performed by changing temperatures from one to another, it is practically impossible to verify or check all the products since the products must be taken in and out of a thermostatic chamber or the products must be held in the thermostatic chamber until they reach to a predetermined stable temperature.
No guarantee with a low temperature and a low voltage or with a high temperature and a high voltage is not given to the products, even if a delay time is measured and determined in the environment of a high temperature and a high voltage. Consequently, the delay time must be determined within a narrow range, which brings about a reduction of yields of the products.
On the contrary, if a valuation basis of the product is relieved so as to improve the yield, for example, by narrowing a usable temperature range and a usable source voltage range or by widening an acceptable delay time, restriction is required about applications and a usable environment of the semiconductor device.
Further, let set values of a semiconductor device be changed by measuring a delay time after the semiconductor device is assembled into a device in a conventional manner, a probe of a tester can not be connected to some of the semiconductor devices or an error is caused to occur in the delay time due to a parasitic capacity of the probe.